There is an increasing need for highly accurate stable clock sources to drive modern digital electronics equipment, especially in the telecommunications sector. For example, the new LTE-A standard in mobile telecommunications requires clock sources operating at a frequency in the order of 100 MHz with a jitter of 100 femtoseconds or less. The jitter represents the high-speed fluctuations from the desired center frequency. The SONET standards OC-3, OC-12 require clock frequencies of 155.52 MHz (OC-3), 622.08 MHz (OC-12) respectively with RMS jitter of in the tens of picoseconds range.
The common way of generating the desired frequency is to derive it from a lower frequency stable source, such as a very stable crystal oscillator, using a phase locked loop (PLL) with a frequency divider in the feedback path. The frequency divider can be integer-based, in which case the output frequency is an integer multiple of the clock frequency, or fractional. A fractional divider generally includes a sigma-delta modulator to modulate the divisor.
One problem with this approach is that the various components within the phase-locked loop introduce noise that manifests itself as jitter or rapid fluctuations in the output signal. Various attempts have been made to solve this problem.
One approach is described in the paper “A Fractional-N Frequency Synthesizer Architecture Utilizing a Mismatch Compensated PFD/DAC Structure for Reduced Quantization-Induced Phase Noise”, IEEE Trans. On Circuit & Systems, November 2003 (SiLabs). This paper describes a technique employing a digital signal processor (DSP) in the loop filter to increase the loop gain and to minimize the jitter and die size. This technique works reasonably well when chip size is not too small. However, at small die sizes, it eventually suffers from interference between analogue and digital circuits on the die.
A multi-die solution is an option, but this solution requires extra inter-die communication lines, which not only increase the manufacturing cost, but also add additional noise. The DSP approach may also introduce extra quantization noise from the Analogue-to-Digital Converter (ADC) and interference from the DSP processor. A high-speed sampling circuit is required to reduce the quantization noise, which in turn increases the manufacturing cost.
Another approach is described in U.S. Pat. No. 8,085,097 (Hittite). This patent employs a high-order steep analog filter to reduce noise, which increases cost. The high order or steep analogue loop further has a stability issue that is sensitive to the individual analogue parameters and makes the precise control over manufacture difficult.
Yet another solution is described in the paper: “A 2.4 GHz Monolithic Fractional-N Frequency Synthesizer With Robust Phase-Switching Prescaler and Loop Capacitance Multiplier”, IEEE Journ. of Solid-State Circuits, June 2003 (Texas Instruments). In this approach, the overall gain is increased through the use of dual loops, which implies double the cost.
The paper entitled “A Low Noise Multi-PFD PLL with Timing Shift Circuit”, IEEE MTT-S International, 2012, describes a PLL with a series of phase/frequency detectors (PFDs) and loop filters arranged in parallel, each PFD-loop filter combination providing a separate input to the voltage controlled oscillator (VCO) of the phase locked loop. The phase comparison of each PFD is time-shifted is to avoid noise correlation. However, this approach is limited by the correlation length, which limits noise removal to a specific reference band. Also, mismatch between each parallel PFD gives rise to implementation difficulties.